Therefore, designing safe and efficient key stream generators is essential for stream cipher operation. For each plain text bit, the corresponding cipher text bit is calculated as some revertible function (usually xor gate) of the plain text bit and the corresponding key stream bit. Many stream cipher architectures require a key stream generator, which is a pseudo random bit generator whose seed is the encryption key. Stream ciphers are ciphers that encrypt plain text characters individually (usually bit by bit), in contrast to block ciphers, which encrypt plain text in large block (64 bits or more). The history of pseudo random number generation in hardware is heavily linked to the development of stream ciphers. In this project, we present a design of the switching generator using Verilog HDL. This new generator has been proven to be resistant to algebraic attacks and side channel attacks, while preserving efficiency and security requirements. In 2015, a new clocked controlled generator, called the switching generator, was proposed. Nevertheless, they remain vulnerable to many attacks such as side channel attacks and algebraic attacks.

These methods include nonlinear combination generators, nonlinear filter generators, and clock controlled generators. Several methods have been proposed to destroy the linearity inherent in LFSR design. However, standard LFSRs are not cryptographically secure, since the output sequence can be uniquely predicted given a small number of key stream bits using Berlekamp-Massey algorithm. Further, they are capable of producing output sequences with large periods and good statistical properties. Linear feedback shift registers are an excellent tool for implementing a pseudo random bit generator in hardware they inhibit a simple and efficient electronic structure.

Linear feedback shift register verilog